Some parallel computing devices include node architectures based upon SOC technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Each ASIC node includes a plurality of processors, which may be used individually or simultaneously, to work on any combination of computations or communications as required by a particular algorithm being solved and executed at any point in time.
Developments in SOC technology have led to an increase in on-chip clock frequencies, the number of transistors on a single chip and the die-size itself. Often however, these increases may also come with a cost of higher power consumption, which increases as chips decrease in size. Some undesired consequences of chip size reduction may be power consumption concentration, which may sometimes result in local chip hotspots, and static power, which often rises exponentially with increasing ambient temperatures. Also, static power may waste chip energy and shorten chip and system lifetimes as well.
Process variation is often described as a type of variation that occurs when there are differences in multiple instances of the same process. For example, at a SOC chip's design stage, certain technical characteristics, such as supply voltage and frequency, may be specified. However, at chip's manufacturing stage, due to imperfections in the manufacturing process, each chip and its components may exhibit different technical characteristics, i.e. variations, other than those specified at the design stage. Process variation may be attributed to various factors such as difference in transistor threshold voltages (VT), effective channel length and oxide thickness in transistors. Consequently, due to process variation, some SOC chips may exhibit different power and thermal behavior despite running similar workloads.